The Inter-Integrated Circuit (I2C) two-wire bus relies on open-drain transceivers pulled high by external resistors. Because the bus is passively pulled up by resistors and actively driven low by FETs, RC charging dynamics dictate the maximum reliable clock speed.
#1. Calculating Minimum and Maximum Pull-Up Resistance
Pull-up resistor values are bounded by two strict electrical constraints: minimum resistance is bounded by the driver's current-sinking capability, while maximum resistance is bounded by the standard's allowable rise time \(t_r\).
- Minimum Pull-Up: \(R_{p,\min} = (V_{DD} - V_{OL}) / I_{OL}\). For \(V_{DD} = 3.3\text{V}\), \(V_{OL} = 0.4\text{V}\), and \(I_{OL} = 3\text{mA}\), \(R_{p,\min} \approx 967\,\Omega\).
- Maximum Pull-Up: \(R_{p,\max} = t_r / (0.8473 \times C_b)\). For 100 kHz Standard-mode (\(t_r \le 1000\text{ns}\)) with 100pF bus capacitance, \(R_{p,\max} \approx 11.8\,\text{k}\Omega\).
- For 400 kHz Fast-mode (\(t_r \le 300\text{ns}\)), \(R_{p,\max}\) drops to \(3.54\,\text{k}\Omega\).
Internal microcontroller pull-ups (typically 30kΩ to 50kΩ) are far too weak for multi-device buses. Always install stiff external pull-ups (2.2kΩ to 4.7kΩ) on SDA and SCL.
#2. DSO Waveform Inspection & Breadboard Parasitics
On a solderless breadboard with multiple sensor modules (OLED display, RTC, current sensor), parasitic trace and tie-point capacitance can easily exceed 60pF. Observing SCL on an oscilloscope with 10kΩ pull-ups revealed exponential RC rise curves failing to reach the 0.7 VDD threshold before the clock half-period expired, triggering bus arbitration faults. Dropping pull-ups to 2.2kΩ reduced rise time to 160ns and eliminated packet loss.