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Engineering Hub

Applying electrical and electronics engineering principles to high-integrity software, digital instrumentation, and real-time interactive systems.

The EEE Perspective

Engineering × Software

My coursework in Electrical & Electronics Engineering at Presidency University provides a rigorous foundation for designing resilient digital architectures. It connects physical physical-layer constraints with high-level software abstractions.

Concepts like signal processing, control feedback loops, state-space modeling, and transient response instill a disciplined methodology for debugging, race-condition mitigation, and low-latency systems.

Rather than static screenshots, the interactive workbench below delivers fully interactive laboratory simulators running on-demand in the browser.

Academic & Bench Focus

Circuit analysisSchematic readingBench instrumentsMicrocontrollersEmbedded CPCB design
69 WidgetsSelf-Contained Simulators
On-Demand JSLazy Loaded & Sandboxed

Flagship Simulators

Primary Laboratory Workbenches

Five core instruments illustrating time-domain signal probing, closed-loop control, frequency response analysis, and active filtering with verified theoretical models.

Flagship InstrumentSignals & Instrumentation

Dual-Trace Digital Oscilloscope

Dual-channel waveform visualization modeling 10X probe impedance (10MΩ || 15pF), Lissajous X-Y phase mode, and real-time Vpp/frequency tracking.

Governing Model & Equation
V(t) = V_p · sin(2πft + φ) + V_offset
Flagship InstrumentControl Systems

PID Closed-Loop Controller

2nd-order underdamped plant feedback loop tuning. Models proportional gain, integral steady-state error elimination, and derivative damping against overshoot.

Governing Model & Equation
u(t) = K_p · e(t) + K_i · ∫e(τ)dτ + K_d · (de/dt)
Flagship InstrumentAnalog & Circuit Theory

Frequency Response Bode Analyzer

Logarithmic decade sweeps plotting magnitude (dB) and phase (degrees). Evaluates -3dB cutoff frequency, gain margin, and phase margin stability.

Governing Model & Equation
f_c = 1 / (2πRC), |H(jω)|_dB = -20 log₁₀ √(1 + (ω/ω_c)²)
Flagship InstrumentDigital Logic & Protocols

8-Channel Digital Logic Analyzer

Multi-channel logic state capture with configurable edge triggers and timing cursors for debugging SPI, I2C, and UART serial protocols.

Governing Model & Equation
T_sample = 1 / f_s, t_hold ≥ t_setup
Flagship InstrumentAnalog Electronics

Sallen-Key Active Filter Simulator

2nd-order Sallen-Key lowpass and highpass active topologies with op-amp gain-bandwidth product (GBWP), slew rate modeling, and -40 dB/decade roll-off.

Governing Model & Equation
f_c = 1 / (2π · √(R₁R₂C₁C₂)), Q = √(R₁R₂C₁C₂) / (C₂(R₁+R₂))

Interactive Workbench

Laboratory Instrument Simulators

Select an instrument or circuit module to launch its dedicated, high-performance interactive workbench.

Dual-Trace Digital Oscilloscope
Signals & Oscilloscopes Core Bench

Dual-Trace Digital Oscilloscope

Signal Processing & Instrumentation

Dual-channel CRT/LCD waveform visualizer with real-time frequency, Vpp amplitude, trigger level, and timebase scaling.

Bandwidth:20 MHz Virtual
Sample Rate:100 MS/s
Interactive Digital Logic Sandbox
Digital Logic Core Bench

Interactive Digital Logic Sandbox

Digital Systems Design

Real-time Boolean gate propagation engine (AND, OR, NOT, NAND, NOR, XOR) with live truth tables and timing waveforms.

Gate Families:TTL 74LS / CMOS 4000
Propagation Delay:< 10ns
Signals & Oscilloscopes

Interactive Signal Visualizer

Signal Processing

Parametric waveform generator contrasting sinusoidal, square, triangle, and sawtooth harmonics with noise injection.

Waveforms:Sine, Square, Triangle, Saw
Frequency Range:1 Hz – 20 kHz
Microcontroller Pinout Explorer
Microcontrollers & IoT Core Bench

Microcontroller Pinout Explorer

Embedded Systems

Interactive hardware pin mapping for ESP32, STM32, Arduino Uno, and Raspberry Pi Pico with GPIO, ADC, PWM, and I2C multiplexing.

Architectures:Xtensa, ARM Cortex-M, AVR, RP2040
Voltage Domains:3.3V / 5.0V Tolerant
Audio Spectrum FFT Visualizer
Audio & Acoustics

Audio Spectrum FFT Visualizer

Acoustics & DSP

Browser Web Audio API Fast Fourier Transform (FFT) visualizer rendering real-time frequency bins from 20 Hz to 20 kHz.

FFT Size:2048 Bins
Smoothing Time:0.85
Digital Logic

Breadboard Circuit Builder

Hardware Prototyping

Virtual solderless breadboard with tie-point terminal strips, power rails, jumper wiring, and integrated LED/resistor probing.

Tie Points:830 Points
Power Rails:Dual ±5V Buses
Microcontrollers & IoT

ESP32 FreeRTOS Firmware Simulator

Firmware Engineering

Dual-core Xtensa simulation demonstrating FreeRTOS tasks, queue scheduling, semaphore locks, and non-blocking sensor acquisition.

CPU Cores:Dual Core @ 240 MHz
RTOS Kernel:FreeRTOS v10.x
Microcontrollers & IoT

3D PCB Layer Stack Explorer

PCB Layout Design

Exploded 3D view of a 4-layer FR-4 circuit board isolating Top Silk, Copper traces, Dielectric Prepreg, Ground Plane, and Solder Mask.

Layer Count:4 Layers
Substrate:FR-4 Tg 150°C
Microcontrollers & IoT

ESP32-WROOM Pinout Matrix

Embedded Systems

Comprehensive 38-pin matrix detailing strapping pins, capacitive touch channels, RTC GPIOs, and flash interface lines.

Flash Size:4 MB QSPI
ADC Channels:18 x 12-bit SAR
Audio & Acoustics

Web Audio Monophonic Synthesizer

Web Audio API

Low-latency software synthesizer featuring VCO waveforms, VCF resonant lowpass filter, ADSR envelope, and LFO modulation.

Oscillator Types:Saw, Square, Triangle, Sine
Filter Slope:-24 dB/Octave 4-Pole
Digital Logic

8-Channel Digital Logic Analyzer

Protocol Debugging

Multi-channel waveform capture engine with configurable edge triggers, timing cursors, and protocol frame decoding.

Channels:8 Channels
Sampling Depth:10,000 Samples
Audio & Acoustics

Interactive Piano Keybed Controller

Audio DSP

Full chromatic keyboard interface with mouse/keyboard mapping, velocity sensitivity, octave transpose, and MIDI event dispatch.

Keys:25-Key 2-Octave Range
Pitch Standard:A4 = 440 Hz
Analog & Circuit Theory

Frequency Response Bode Plot Simulator

Control Systems

Dual magnitude (dB) and phase angle (degrees) logarithmic frequency plot for evaluating stability margins and bandwidth.

Frequency Span:10 Hz – 1 MHz
Gain Margin:Calculated dB
Digital Logic

3D Perspective Logic Gate Simulator

Visual Computing

3D spatial logic visualizer mapping inputs, gate propagation, and electron particle flows across three-dimensional axes.

Rendering:Perspective 3D Canvas
Visual Cues:Current Glow & Particle Paths
Signals & Oscilloscopes

Precision Function Generator

Test & Measurement

Bench instrument generating clean test signals with precise DC offset, duty cycle modulation, and sweep frequency sweeps.

Waveforms:Sine, Square, Ramp, Pulse
Amplitude:0 – 10 Vpp
Neural Network Topology Visualizer
Control & Modeling

Neural Network Topology Visualizer

Machine Learning & AI

Interactive multi-layer perceptron showing forward propagation weights, ReLU activation nodes, and backprop gradient descent.

Layers:Input, 2 Hidden, Output
Activations:ReLU, Sigmoid, Softmax
PID Closed-Loop Controller Simulator
Control & Modeling Core Bench

PID Closed-Loop Controller Simulator

Control Systems Engineering

Proportional-Integral-Derivative feedback loop tuning workbench with step response tracking, overshoot, and steady-state error.

Gains:Kp, Ki, Kd Fine Controls
System Model:2nd-Order Underdamped
Microcontrollers & IoT

CAN Bus & UART Protocol Analyzer

Automotive & Industrial Serial

Differential CAN High/Low signal inspection and asynchronous UART packet framing with baud rate matching and parity checks.

CAN Protocol:CAN 2.0B 29-bit Identifiers
Baud Rates:125k, 250k, 500k, 1 Mbps
API & DSP Latency Benchmark Simulator
Control & Modeling

API & DSP Latency Benchmark Simulator

Systems Performance

Real-time benchmark comparing HTTP/2 vs HTTP/3 QUIC connection establishment, payload serialization, and edge TTFB latency.

Protocols:HTTP/1.1, HTTP/2, HTTP/3 QUIC
Payload Sizes:1 KB – 5 MB
Microcontrollers & IoT

SMD Component Placement & Thermal Inspector

Electronics Manufacturing

Component packaging inspector comparing 0402, 0603, 0805, QFN, and BGA footprint clearances and reflow solder thermal profiles.

Packages:0402 to QFP-64
Reflow Peak:245°C Lead-Free SAC305
Audio & Acoustics

Parametric Audio Equalizer & Biquad Filter

Digital Signal Processing

Multi-band parametric EQ using cascaded biquad IIR filters with interactive Q factor resonance and gain peaking.

Filter Architecture:Biquad IIR Transposed Direct Form II
Bands:5 Parametric Bands
NE555 Precision Timer (Astable & Monostable)
Analog & Circuit Theory Core Bench

NE555 Precision Timer (Astable & Monostable)

Analog Circuit Design

Interactive 555 timer IC with internal comparator thresholds (1/3 Vcc and 2/3 Vcc), discharge transistor, and RC timing math.

Operational Modes:Astable Multivibrator / Monostable
Threshold Voltages:1/3 Vcc (Trigger), 2/3 Vcc (Threshold)
Fourier Series Harmonic Synthesizer
Signals & Oscilloscopes Core Bench

Fourier Series Harmonic Synthesizer

Signal Processing & Mathematics

Reconstruct arbitrary periodic waveforms by summing fundamental and odd/even harmonics with Gibbs phenomenon visualization.

Harmonics:1st through 25th Harmonic
Mathematical Basis:f(t) = a0/2 + ∑ [an cos(nωt) + bn sin(nωt)]
RLC Transient Circuit Response
Analog & Circuit Theory Core Bench

RLC Transient Circuit Response

Transient Analysis

Second-order differential equation solver modeling series RLC circuits across Underdamped, Critically Damped, and Overdamped states.

Damping Factor (ζ):ζ < 1 (Under), ζ = 1 (Critical), ζ > 1 (Over)
Resonant Frequency:ω0 = 1 / √(L·C)
Analog & Circuit Theory Core Bench

Op-Amp Active Filter Simulator

Analog Electronics

Sallen-Key active lowpass and highpass filter topologies with gain-bandwidth product (GBWP), slew rate limits, and roll-off.

Topologies:Sallen-Key, Multiple-Feedback (MFB)
Roll-off Rate:-40 dB/Decade (2nd Order)
Analog & Circuit Theory

4/5-Band Resistor Color Code Calculator

Laboratory Essentials

Decodes through-hole resistor color bands into nominal resistance, multiplier, and manufacturing tolerance percentages.

Color Bands:4-Band & 5-Band Support
Tolerances:±1%, ±2%, ±5%, ±10%
Ohm's Law & Power Dissipation Calculator
Analog & Circuit Theory

Ohm's Law & Power Dissipation Calculator

Basic Circuit Theory

Instantaneous multi-variable solver for Voltage (V), Current (I), Resistance (R), and Power (P = V·I = I²·R = V²/R).

Variables:Voltage, Current, Resistance, Power
Units:Standard SI Units (V, A, Ω, W) with SI prefixes
Analog & Circuit Theory

RC Passive Lowpass/Highpass Filter

Passive Filters

First-order RC passive filter simulator calculating -3dB cutoff frequency (fc = 1 / 2πRC) and attenuation across octaves.

Order:1st Order Passive (-20 dB/Decade)
Cutoff Point:-3.01 dB at fc
Signals & Oscilloscopes Core Bench

Three-Phase Phasor & AC Power Vector Analyzer

Three-Phase Power Systems

Interactive rotating polar phasor diagram and line-to-line 3-phase instantaneous AC sinusoidal waveforms with live active/reactive power calculations.

Phase Separation:120° (2π/3 radians)
Line Relation:VL = √3 · Vph (Star Connection)
Analog & Circuit Theory Core Bench

AC-DC Full-Wave Rectifier & Filter Workbench

Power Electronics & Rectification

Diode bridge conduction simulator with capacitive ripple filtering, diode threshold voltage drops (1.4V), and peak-to-peak ripple voltage calculations.

Topologies:Full-Wave Bridge (4 Diodes) / Half-Wave
Diode Drop:2 · 0.7V = 1.4V (Full-Wave Bridge)
Control & Modeling Core Bench

Synchronous Buck DC-DC Converter Simulator

Switched-Mode Power Electronics

Switched-mode step-down DC-DC power supply with PWM duty modulation, inductor current triangular ripple (CCM/DCM), and output ripple filtering.

Duty Cycle:D = Vout / Vin
Inductor Ripple:ΔIL = (Vin - Vout) · D / (L · fsw)
Analog & Circuit Theory Core Bench

Semiconductor Bandgap & Carrier Dynamics

Solid State Physics & Electronic Materials (PHY1001)

Interactive energy band model visualizing valence/conduction bands, Fermi level, thermal carrier excitation ratio, and donor/acceptor impurity states across Si, Ge, GaAs, InP, SiC, and Diamond.

Materials:Si, Ge, GaAs, InP, SiC, Diamond
Excitation Law:n/N = exp(-Eg / 2kT)
Control & Modeling Core Bench

Linear Algebra & Systems Solver

Engineering Mathematics (MAT1001)

Interactive 3x3 matrix computation engine performing row echelon reduction, rank determination, Gauss elimination, and characteristic eigenvalue analysis with quadratic form definiteness.

Dimension:3x3 Linear Systems
Algorithms:Row Echelon, Gauss Elimination
Control & Modeling Core Bench

Statics Equilibrium & Decision Matrix

Foundations of Engineering (CIV1200)

Interactive 2D Free Body Diagram vector engine modeling equilibrium, normal reaction, and string tension alongside a weighted multi-criteria engineering design decision matrix.

Equilibrium Law:ΣFx = 0, ΣFy = 0
Contact Reaction:R = mg - T·sin(θ)
Control & Modeling Core Bench

1D Quantum Well & Wavefunction Simulator

Quantum Physics & Advanced Materials (PHY1001)

Interactive 1D infinite potential well solver computing discrete energy eigenvalues En, stationary wavefunctions ψn(x), and spatial probability densities |ψn(x)|² across semiconductor heterostructures.

Governing Law:-ħ²/(2m) d²ψ/dx² = Eψ
Energy Levels:En = n²h² / (8mL²)
Control & Modeling Core Bench

Beam Equilibrium & SFD / BMD Solver

Structural Mechanics & Statics (CIV1200)

Interactive structural beam analysis engine computing support reactions, piecewise shear force diagrams (SFD), and parabolic bending moment diagrams (BMD) under point and distributed loads.

Differential Law:dV/dx = -w, dM/dx = V
Support Types:Simply Supported (Pin-Roller), Cantilever
Control & Modeling Core Bench

B-H Magnetic Hysteresis & Core Loss Simulator

Magnetic & Dielectric Materials (PHY1001)

Real-time B-H hysteresis loop engine computing domain remanence (Br), coercivity (Hc), saturation (Bs), and cyclic thermal dissipation across transformer steels, ferrites, and rare-earth magnets.

Governing Law:B = μ0(H + M) = μr μ0 H
Energy Loss:Wh = ∮ H dB (J/m³·cycle)
Control & Modeling Core Bench

Mechanics of Materials: Stress-Strain & Deformation Solver

Mechanics of Materials (CIV1200)

Interactive tensile testing simulator calculating engineering stress, strain, Hooke's law elongation, Poisson contraction, ductile vs brittle curves, and structural Factor of Safety (FOS).

Normal Stress:σ = P / A0 (MPa)
Axial Elongation:ΔL = (P L0) / (A0 E)
Control & Modeling Core Bench

Multiple Integrals & Slicing Transformation Visualizer

Calculus & Coordinate Systems (MAT1001)

Interactive multiple integration lab demonstrating Fubini's change of integration order (Type I vs Type II planar slicing) and polar metric transformations (r dr dθ) on cardioid and circular boundaries.

Planar Slicing:Type I (Vertical dx dy) vs Type II (Horizontal dy dx)
Polar Area Element:dA = r dr dθ (Jacobian r)
Control & Modeling Core Bench

Multivariable Extrema & Hessian Surface Visualizer

Differential Calculus & Extrema (MAT1001)

Interactive scalar field curvature analyzer computing Hessian matrix determinants (Δ = AC - B²), eigenvalues, and 2D contour/3D wireframe projections to classify local minima, maxima, and saddle points.

Governing Hessian:H = [[A, B], [B, C]] where A=f_xx, B=f_xy, C=f_yy
Discriminant:Δ = AC - B² (det(H))
Control & Modeling Core Bench

Second-Order RLC Transient & s-Domain Pole Simulator

Circuit Analysis & Synthesis (EEE2001)

Interactive transient response and complex s-plane pole trajectory analyzer computing attenuation factor (α), undamped resonant frequency (ω₀), damping ratio (ζ), and capacitor step response across underdamped, critical, and overdamped regimes.

Characteristic Eq:s² + 2αs + ω₀² = 0 where α = R/(2L)
Natural Frequency:ω₀ = 1 / √(LC)
Control & Modeling Core Bench

First-Order ODE & Transient Relaxation Lab

Calculus & Differential Equations (MAT1001)

Interactive step response and exponential relaxation simulator for first-order linear ordinary differential equations, modeling RL inductors, RC capacitors, and Newton's law of cooling with real-time 1τ (63.2%) and 5τ settling metrics.

Governing ODE:dy/dt + P(t)y = Q(t) with IF = exp(∫ P dt)
Step Solution:y(t) = y_ss + (y_0 - y_ss) · exp(-t / τ)
Control & Modeling Core Bench

Laser Cavity & Optical Fiber Waveguide Simulator

Engineering Physics & Optoelectronics (PHY1001)

Interactive ray-tracing waveguide engine calculating Snell's law refraction, Total Internal Reflection (TIR), critical angle (θc), numerical aperture (NA), normalized frequency (V-number) single-mode cutoff, and dB link losses.

Numerical Aperture:NA = √(n₁² - n₂²) = sin(θ_a)
Critical Angle:sin(θ_c) = n₂ / n₁
Control & Modeling Core Bench

Shaft Torsion & Thin Cylinder Pressure Simulator

Engineering Mechanics & Structures (CIV1200)

Dual-mode mechanical stress engine simulating solid/hollow shaft pure torsion shear stress gradient (T/J = τ/r), polar modulus (Zp), power transmission, and thin-walled cylinder circumferential (hoop) vs longitudinal membrane stresses.

Torsion Formula:T/J = τ/r = Gθ/L
Polar Modulus:Z_p = πd³ / 16 (Solid), π(D⁴ - d⁴) / (16D) (Hollow)
Analog & Circuit Theory Core Bench

Two-Port Network Parameter Matrix & Attenuator Analyzer

Electric Circuit Analysis & Synthesis (EEE2001)

Interactive multi-parameter two-port synthesis engine evaluating [Z], [Y], [ABCD], and [h] matrices, reciprocity (AD - BC = 1), symmetry (A = D), T-pad/Pi-pad attenuation, and loaded driving-point impedances.

Matrix Formulations:[Z], [Y], [ABCD], and [h]
Reciprocity Proof:AD - BC = 1 (Passive Bilateral)
Analog & Circuit Theory Core Bench

Network Functions, Complex s-Plane & Bode Resonator Simulator

Electric Circuit Analysis & Synthesis (EEE2001)

Interactive rational s-domain transfer function analyzer mapping poles, zeros, and Hurwitz stability to steady-state frequency response Bode curves and transient step damping dynamics.

Transfer Form:H(s) = N(s) / [s² + 2ζω₀s + ω₀²]
Stability Test:Hurwitz Criterion (All poles in LHP)
Analog & Circuit Theory Core Bench

Passive Network Synthesis: Foster & Cauer Realizations

Electric Circuit Analysis & Synthesis (EEE2001)

Interactive immittance synthesis engine expanding Positive Real (PR) LC rational driving-point functions into Cauer I & II ladder networks and Foster I & II tank realizations.

Synthesis Forms:Foster I, Foster II, Cauer I, and Cauer II
Reactance Theorem:dX/dω > 0 (Strict Interlacing)
Analog & Circuit Theory Core Bench

BJT Biasing, Q-Point & Small-Signal CE Amplifier Analyzer

Analog Electronic Circuits (EEE2002)

Interactive DC/AC load line engine computing voltage-divider operating point (Q-point), thermal stability factor (S), and dynamic small-signal AC gain with saturation/cutoff waveform clipping.

Biasing Topology:Self-Bias / Voltage-Divider Network (R1, R2, RC, RE)
Operating Limits:IC(sat), VCE(cutoff), Q-Point (VCEQ, ICQ)
Analog & Circuit Theory Core Bench

High-Frequency BJT Amplifier & Miller Effect Bode Analyzer

Analog Electronic Circuits (EEE2002)

Interactive 8-decade wideband frequency response visualizer computing low cutoff poles (fLs, fLc, fLe), high cutoff poles via Miller capacitance expansion, fT unity-gain frequency, and Gain-Bandwidth Product.

Bode Frequency Span:1 Hz to 1 GHz (Logarithmic 8 Decades)
Parasitic Capacitances:Cπ (base-emitter), Cμ (collector-base feedback)
Analog & Circuit Theory Core Bench

Feedback Amplifiers & Sinusoidal Oscillators Lab

Analog Electronic Circuits (EEE2002)

Interactive Barkhausen criterion laboratory with 4 negative feedback topologies (Series/Shunt) and 5 precision oscillators (Wien Bridge, RC Phase Shift, Colpitts, Hartley, Quartz Crystal) featuring real-time oscilloscope startup transients.

Barkhausen Criterion:|Aβ| = 1.0, ∠Aβ = 0° (or 360°)
Oscillator Topologies:Wien Bridge, RC Phase Shift, Colpitts, Hartley, Crystal
Analog & Circuit Theory Core Bench

Operational Amplifiers & Active Applications Lab

Analog Electronic Circuits (EEE2002)

Interactive op-amp laboratory covering linear precision processing (Inverting, Non-Inverting, 3-Op-Amp InAmp with CMRR, Integrator/Differentiator), 2nd-order active Sallen-Key filters, and nonlinear Schmitt triggers / Superdiode precision rectifiers.

Linear Circuits:Inverting, Non-Inverting, InAmp (CMRR), Integrator, Differentiator
Active Filters:2nd-Order Sallen-Key Lowpass, Highpass, Bandpass (-40 dB/dec)
Electrical Machines & Power Systems Core Bench

Single-Phase Transformer & Phasor Lab

Electrical Machines I (EEE2003)

Interactive transformer engineering laboratory featuring referred equivalent circuits, interactive phasor diagrams (lagging/unity/leading loads), efficiency vs load fraction curves, and simulated OC/SC test benches.

Equivalent Parameters:R01, X01 (HV referred) / R02, X02 (LV referred)
Phasor Diagram:V2, I2, I2·R02, jI2·X02, V1' with power factor angle
Electrical Machines & Power Systems Core Bench

Three-Phase Transformers & Auto-Transformers Lab

Electrical Machines I (EEE2003)

Interactive power engineering laboratory exploring 3-phase vector groups (Dyn11, Yd1, Yy0), Open-Delta (V-V) emergency capacity derating, Scott-T 3Φ-to-2Φ orthogonal transformation, and Auto-Transformer copper savings.

Vector Groups:Dyn11, Yd1, Yy0, Dd0 with clock phasor dial (30° steps)
Open-Delta (V-V):57.7% bank capacity derating, cos(30° ± φ) unit loading
Electrical Machines & Power Systems Core Bench

DC Generators & Armature Reaction Lab

Electrical Machines I (EEE2003)

Interactive DC machine generator laboratory analyzing EMF equations (Lap vs Wave windings), Open-Circuit Characteristic (OCC) self-excitation build-up, critical field resistance (Rc), armature reaction MNA shift, and external load curves.

EMF Generation:E = (Φ·Z·N·P) / (60·A) with Lap (A=P) vs Wave (A=2) paths
OCC Build-Up:Non-linear magnetization curve, Rf line slope, Critical Rc threshold
Electrical Machines & Power Systems Core Bench

DC Motors, Speed Control & Testing Lab

Electrical Machines I (EEE2003)

Interactive DC motor engineering laboratory featuring torque-speed characteristics (Shunt droop vs Series runaway), speed control methods (Field flux weakening & Armature resistance), Ward-Leonard drive, 4-point starter, and virtual Swinburne / Hopkinson test runs.

Governing Law:Eb = V - Ia·Ra (Natural speed governor), T = 0.159·Φ·Z·Ia·(P/A)
Torque-Speed:Shunt constant-speed vs Series hyperbolic (T ∝ Ia²) runaway warning
Electromagnetics & Field Theory Core Bench

Vector Fields, Del Calculus & Electrostatic Mapping Lab

Electromagnetic Field Theory (EEE2004)

Interactive electromagnetic field theory laboratory featuring vector field calculus (Divergence ∇·F and Curl ∇×F), electrostatic point charge mapping, equipotential contour generation, and Gauss's law enclosed surface flux integration.

Vector Calculus:Divergence (∇·E), Curl (∇×E = 0 for static), Potential Gradient (E = -∇V)
Charge Mapping:Monopole (+Q), Electric Dipole (+/-Q pair), Equipotential contours
Electromagnetics & Field Theory Core Bench

Electrostatic Fields, Gauss's Law & Dielectric Refraction Lab

Electromagnetic Field Theory (EEE2004)

Interactive 2D spatial electrostatic vector field simulator mapping E = -∇V, equipotential contour rings, closed Gaussian surface flux integration (∮ D · dA = Qenc), and dielectric boundary refraction across varying relative permittivities.

Vector Field:E = -∇V spatial arrows with magnitude color-coding
Equipotential:Orthogonal constant potential contours V = q / (4πεr)
Electromagnetics & Field Theory Core Bench

Magnetostatics, Biot-Savart Law & Ampère Loop Integrator

Electromagnetic Field Theory (EEE2004)

Interactive 2D/3D magnetostatic simulation suite exploring the Biot-Savart law for wires, loops, and solenoids, closed Ampèrian loop line integration (∮ H · dL = Ienc), parallel Lorentz wire forces, and magnetic boundary refraction across media interfaces.

Biot-Savart Engine:Concentric B-field rings, loop on-axis Bz(z), & solenoid core
Ampère Loop:∮ H · dL = Ienc closed numerical line integrator
Electromagnetics & Field Theory Core Bench

Maxwell's Equations & Uniform Plane Wave Propagation Lab

Electromagnetic Field Theory (EEE2004)

Interactive 3D/2D electrodynamic simulation suite demonstrating transverse electromagnetic (TEM) wave propagation, real-time Poynting power vector flow, loss tangent & skin depth penetration in conductors, wave polarization (linear, circular RHCP/LHCP, elliptical), and normal interface reflection/VSWR standing waves.

Plane Waves:Orthogonal E-field, H-field & Poynting power flow S = E × H
Skin Depth:Conductor current decay J(z) = J0 e^(-z/δ) & surface resistance Rs
Control Systems & Automation Core Bench

Control System Modeling, Block Diagram & Signal Flow Lab

Control Systems Engineering (EEE2005)

Interactive control engineering suite demonstrating mathematical modeling of physical systems, Force-Voltage (F-V) and Force-Current (F-I) analogies, canonical block diagram reduction algebra, Mason's gain formula for signal flow graphs, and complex s-plane pole-zero stability mapping.

Physical Analogs:Force-Voltage (M ↔ L) & Force-Current (M ↔ C) dualities
Block Algebra:Interactive cascade, parallel, feedback, and minor loop reduction
Circuit Theory & Electromagnetics Core Bench

DC Circuits, Network Theorems & Electromagnetic Induction Lab

Basics of Electrical & Electronics (EEE1200)

Comprehensive interactive laboratory suite for DC circuits: series-parallel resistor reduction, voltage & current divider rules, electrical shock & bird on wire safety paradox, bidirectional Star-Delta (Y-Δ) conversion, Faraday dynamic Blv sinθ & static N dΦ/dt induction, and coupled coils with mutual inductance M = k√(L1 L2).

DC Networks:Series, parallel, and ladder network analysis with KVL & KCL verification
Star-Delta:Bidirectional Y ↔ Δ conversion with terminal impedance equivalence
Circuit Theory & Power Systems Core Bench

AC Circuits, Phasors & Three-Phase Star/Delta Lab

Basics of Electrical & Electronics (EEE1200)

Interactive laboratory suite for AC circuits: sinusoidal waveform generation, RMS and average mid-ordinate decomposition, pure R, L, C and series R-L circuits, rotating phasor vector diagrams, 2f instantaneous power waves, power triangle with capacitor power factor correction, and balanced Star (Y) vs. Delta (Δ) 3:1 power ratio analysis.

AC Metrics:Cycle, period, frequency, RMS (0.707 Vm), Average (0.637 Vm), Form & Peak factors
Phasors & R-L:Rotating phasor vector plane, impedance triangle Z² = R² + XL², and 2f power oscillations
Control Systems & Automation Core Bench

Control Systems Time Response & Transient Specifications Lab

Control Systems Engineering (EEE2005)

Interactive laboratory exploring second-order prototype dynamics (undamped, underdamped, critically damped, and overdamped regimes), transient performance specifications (delay, rise, peak time, %Mp, and settling time), steady-state error (ess) across System Types 0, 1, and 2, and complex s-plane pole placement with dominant pole approximation.

Second-Order Dynamics:Step, impulse, and ramp responses across damping ratios 0 ≤ ζ ≤ 2.5
Transient Specs:td, tr, tp, %Mp = e^(-πζ/√(1-ζ²)), and ts (2% & 5% tolerance bands)
Control Systems & Automation Core Bench

Control Systems Stability Analysis & Root Locus Lab

Control Systems Engineering (EEE2005)

Interactive laboratory exploring system stability criteria (BIBO and asymptotic), the Routh-Hurwitz array builder with special cases (first-column zero and row of zeros / auxiliary polynomials), Evans root locus construction rules with dynamic gain exploration, and allowable s-plane pole placement regions.

Routh Array Engine:Live array computation, sign changes, marginal gain Kcrit, and oscillation frequency ωosc
Evans Rules:Real-axis segments, asymptote centroid σa, departure angles φd, and breakaway points dK/ds = 0
Control Systems & Automation Core Bench

Frequency Response & State Variable Analysis Lab

Control Systems Engineering (EEE2005)

Interactive laboratory exploring frequency response techniques (Bode magnitude and phase plots, gain margin, phase margin, crossover frequencies), polar and Nyquist encirclement stability criteria (N = P - Z), state-space canonical representations, State Transition Matrix (STM), and Kalman controllability/observability rank tests.

Bode Analysis:Logarithmic frequency sweep (0.1 to 100 rad/s), Gain Margin (GM), and Phase Margin (PM)
Nyquist Criterion:Polar plots, critical point (-1, j0) proximity, and Cauchy argument encirclements N = P - Z
Signal Processing & Communication Core Bench

Signal Operations & System Properties Workbench

Signals and Systems (EEE2006)

Interactive laboratory exploring continuous and discrete signal operations (time shifting, time scaling, reversal, amplitude gain), orthogonal even and odd signal decomposition, energy vs. power signal classification with live integral solvers, and 6 core system axiom evaluations (linearity, time invariance, causality, BIBO stability, memory, and invertibility).

Signal Operations:Continuous time shifting t - t0, scaling x(at), reversal x(-t), and order precedence
Even / Odd Slices:x(t) = xe(t) + xo(t) orthogonal decomposition with energy conservation Ex = Exe + Exo
Signal Processing & Communication Core Bench

LTI Systems, Continuous & Discrete Convolution Workbench

Signals and Systems (EEE2006)

Interactive laboratory exploring continuous-time convolution integral y(t) = ∫x(τ)h(t-τ)dτ via the graphical flip-and-shift method with dynamic overlap area shading, discrete-time convolution sum y[n] = ∑x[k]h[n-k] with sliding stem plots, step response derivation s(t) = ∫h(τ)dτ, and LTI causality and BIBO stability criteria.

CT Convolution:Real-time flip-and-shift y(t) = ∫x(τ)h(t-τ)dτ with overlap area integration
DT Convolution:Sliding sequence stem plots verifying discrete convolution and Ly = Lx + Lh - 1 length rule
Signal Processing & Communication Core Bench

Continuous & Discrete Fourier Analysis & Frequency Response Lab

Signals and Systems (EEE2006)

Interactive laboratory exploring Continuous-Time Fourier Series (CTFS) harmonic synthesis with Gibbs phenomenon analysis, Continuous-Time Fourier Transform (CTFT) time-frequency duality, Discrete-Time Fourier Transform (DTFT) 2π-periodicity, and LTI frequency response H(jω) active filtering.

CTFS Synthesizer:Harmonic summation up to N=25 with exact 8.95% Gibbs overshoot tracking
CTFT Duality:Real-time uncertainty law: time compression induces frequency expansion
Signal Processing & Communication Core Bench

Bilateral Laplace & Z-Transform Pole-Zero Stability Workbench

Signals and Systems (EEE2006)

Interactive multi-domain laboratory exploring continuous s-plane and discrete z-plane pole-zero geometry, Region of Convergence (ROC) topology, BIBO stability theorems, and the conformal mapping z = e^(s Ts).

s-Plane Analysis:Complex pole-zero placement with ROC half-plane/strip shading & jω stability check
z-Plane Analysis:Discrete pole placement with Unit Circle |z|=1 & annular ROC stability evaluation

Bench Notes

Engineering Observations

Empirical laboratory records, network theorems, and hardware characterization notes from active bench experimentation.

Circuit TheoryNetwork Analysis
Verified Bench Lab

Series and parallel networks

Equivalent resistance reduction, Kirchhoff's laws (KCL/KVL), and Thévenin-Norton theorem transformations on bridge networks to calculate impedance matching and power dissipation limits.

∫Req = (R1 · R2)/(R1 + R2) + R3
Interactive Bench Visual
Bridge-Tee ReductionReq = 4.70 kΩ
R1 2.2kR2 5kR3 5kVinVout
Hover components to probe nodal voltagesKCL/KVL BALANCED
R_equivalent4.70 kΩ
Max Power TransferRL = Rth
Tolerance±1% Metal Film
Device PhysicsSemiconductors
Lab Measured

Diode characteristics

Empirical Shockley diode equation verification, contrasting Silicon 1N4148/1N4007 forward knee voltage (Vf ≈ 0.68V) with Schottky 1N5819 (Vf ≈ 0.28V) and reverse recovery time.

∫I = Is · [exp(qV / ηkT) - 1]
Interactive Bench Visual
V-I Exponential Transfer CurveVf = 0.70 V → If = 8.3 mA
Knee (0.68V)If (mA)Vf (V)
Bias:
CONDUCTION ON
V_forward (Si)0.68 V @ 10mA
Reverse Recovery (trr)4.0 ns (Fast)
Zener BreakdownVz = 5.1 V
Analog ElectronicsPower Systems
Schematic Routed

Power supply block diagram

Four-stage linear AC-DC power conversion: step-down center-tapped transformer, full-wave bridge rectifier, bulk reservoir capacitor filter (2200μF), and LM7805 regulator.

∫V_ripple = I_load / (2 · f · C)
Interactive Bench Visual
4-Stage DC Rail Architecture5.00V ± 20mV
230V AC 50Hz Mains Sine WaveSTAGE 1/5
DC Output5.00 V ± 20mV
Ripple Voltage14.2 mV pk-pk
PSRR> 68 dB @ 100Hz
Hardware EngineeringDocumentation
Spec Certified

Component datasheets

Critical pinouts, absolute maximum ratings, junction-to-case thermal resistance (Rθjc), and decoupling capacitor layout guidelines for bench ICs: NE555, LM7805, and ESP32.

∫Tj = Tamb + (Pd · θja)
Interactive Bench Visual
IC Pinout & Thermal Index
P1GND
P2TRIG
P3OUT
P4RESET
P5CTRL
P6THRES
P7DISCH
P8VCC
DIP-8 Precision TimerSPEC VERIFIED
Thermal Budgetθja = 65 °C/W
Decoupling Cap100nF X7R Ceramic
ESD Protection±2 kV HBM

Explore Applied Engineering Projects

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